D flip-flops are a highly used low-level function in microprocessor devices. In order to facilitate testing of microprocessor devices comprising many thousands of such flip-flops, these flip-flops include scan circuitry to provide a means for initializing logic in a desired state. With the scan hardware included in the flip-flop, it becomes possible with a minimum of additional test hardware, to fully determine the state of a microprocessor function by scanning in desired logic patterns from the external pins of the device. By this means testing may be carried out with a greatly reduced test pattern suite.
As more advanced higher speed architectures are developed, microprocessor logic will likely become more complex and concerns about power dissipation will increase. The challenge for the designer remains one of obtaining this higher speed performance while keeping the power dissipation at the lowest possible level. Techniques for power reduction in scannable flip-flops are of prime importance because these functions represent a large portion of the microprocessor device low-level functional blocks.
FIG. 1 illustrates a conventional scannable D flip-flop of prior art. The input logic 120 includes inverters 103 and 106, and transmission gates 104 and 105. This is a typical implementation for current designs. Transmission gate (TG) 104 is ON and transmission 105 is OFF when scan—z is 1 allowing the input data D 101 enter the master latch through gates 104, 106, and 108 when the clock signal CLK is 0. Transmission gate 105 is ON and transmission 104 is OFF when scan—z is 0. This couples input logic 125 to master latch 110 input by transmission gate 108. Master latch 110 and slave latch 114 are connected by transmission gate 112. Slave latch 114 is coupled to data output Q 117 by inverter 115 and is also coupled to the data output SQ 118 by inverter 116.
FIG. 2 illustrates the waveforms for this conventional scannable D flip-flop in the normal operating mode where scan—z is 1. The active positive edge of input clock (CLK) 107, 113 occurs at times 201 and 202. On these positive edges, data is transferred from data input D 101 to data output Q 117. Propagation delay between clock nodes 107, 113 to output Q 117 is denoted by time interval 203 for propagation of a logical 1 and by time interval 204 for propagation of a logical 0. Because the path to scan output SQ 118 is virtually the same as that to data output Q 117, scan output SQ 118 is shown to have an identical response as data output Q 117.
FIG. 3 illustrates the waveforms for the conventional scannable D flip-flop of FIG. 1 in scan mode where scan—z is 0. The active positive edge of input clock (CLK) 107, 113 occurs at times 301 and 302. On these positive edges, data is transferred from scan data input SD 102 to scan output SQ 118. Propagation delay between clock nodes 107 and 113 to scan output SQ 117 is denoted in FIG. 3 by time interval 303 for propagation of a logical 1 and by time interval 304 for propagation of a logical 0. Because the path to data output Q 117 is virtually the same as that to scan output SQ 118, the data output Q 117 is shown to have an identical response as data output SQ 118. Note that in the scan mode the data input 101 may be in an indeterminate state and it has no affect on the result.